Tag: AIArchitecture

vLLM Features

Posted on by lechuck park

vLLM Features & Architecture Breakdown

This chart outlines the key components of vLLM (Virtual Large Language Model), a library designed to optimize the inference speed and memory efficiency of Large Language Models (LLMs).

1. Core Algorithm

  • PagedAttention
    • Concept: Applies the operating system’s (OS) virtual memory paging mechanism to the attention mechanism.
    • Benefit: It resolves memory fragmentation and enables the storage of the KV (Key-Value) cache in non-contiguous memory spaces, significantly reducing memory waste.

2. Data Unit

  • Block (Page)
    • Concept: The minimum KV cache unit with a fixed token size (e.g., 16 tokens).
    • Benefit: Increases management efficiency via fixed-size allocation and minimizes wasted space (internal fragmentation) within slots.
  • Block Table
    • Concept: A mapping table that connects Logical Blocks to Physical Blocks.
    • Benefit: Allows non-contiguous physical memory to be processed as if it were a continuous context.

3. Operation

  • Pre-allocation (Profiling)
    • Concept: Reserves the maximum required VRAM at startup by running a dummy simulation.
    • Benefit: Eliminates the overhead of runtime memory allocation/deallocation and prevents Out Of Memory (OOM) errors at the source.

4. Memory Handling

  • Swapping
    • Concept: Offloads data to CPU RAM when GPU memory becomes full.
    • Benefit: Handles traffic bursts without server downtime and preserves the context of suspended (waiting) requests.
  • Recomputation
    • Concept: Recalculates data instead of swapping it when recalculation is more cost-effective.
    • Benefit: Optimizes performance for short prompts or in environments with slow interconnects (e.g., PCIe limits).

5. Scheduling

  • Continuous Batching
    • Concept: Iteration-level scheduling that fills idle slots immediately without waiting for other requests to finish.
    • Benefit: Eliminates GPU idle time and maximizes overall throughput.

Summary

  1. vLLM adapts OS memory management techniques (like Paging and Swapping) to optimize LLM serving, solving critical memory fragmentation issues.
  2. Key technologies like PagedAttention and Continuous Batching minimize memory waste and eliminate GPU idle time to maximize throughput.
  3. This architecture ensures high performance and stability by preventing memory crashes (OOM) and efficiently handling traffic bursts.

#vLLM #LLMInference #PagedAttention #AIArchitecture #GPUOptimization #MachineLearning #SystemDesign #AIInfrastructure

With Gemini

Basic LLM Workflow

Posted on by lechuck park

Basic LLM Workflow Interpretation

This diagram illustrates how data flows through various hardware components during the inference process of a Large Language Model (LLM).

Step-by-Step Breakdown

① Initialization Phase (Warm weights)

  • Model weights are loaded from SSD → DRAM → HBM (High Bandwidth Memory)
  • Weights are distributed and shared across multiple GPUs

② Input Processing (CPU tokenizes/batches)

  • CPU tokenizes input text and processes batches
  • Data is transferred through DRAM buffer to GPU

③ GPU Inference Execution

  • GPU performs Attention and FFN (Feed-Forward Network) computations from HBM
  • KV cache (Key-Value cache) is stored in HBM
  • If HBM is tight, KV cache can be offloaded to DRAM or SSD

④ Distributed Communication (NvLink/Infiniband)

  • Intra-node: High-speed communication between GPUs via NvLink (with NVSwitch if available)
  • Inter-node: Parallel communication through InfiniBand or NCCL

⑤ Post-processing (CPU decoding/post)

  • CPU decodes generated tokens and performs post-processing
  • Logs and caches are saved to SSD

Key Characteristics

This architecture leverages a memory hierarchy to efficiently execute large-scale models:

  • SSD: Long-term storage (slowest, largest capacity)
  • DRAM: Intermediate buffer
  • HBM: GPU-dedicated high-speed memory (fastest, limited capacity)

When model size exceeds GPU memory, strategies include distributing across multiple GPUs or offloading data to higher-level memory tiers.

Summary

This diagram shows how LLMs process data through a memory hierarchy (SSD→DRAM→HBM) across CPU and GPU components. The workflow involves loading model weights, tokenizing inputs on CPU, running inference on GPU with HBM, and using distributed communication (NvLink/InfiniBand) for multi-GPU setups. Memory management strategies like KV cache offloading enable efficient execution of large models that exceed single GPU capacity.

#LLM #DeepLearning #GPUComputing #MachineLearning #AIInfrastructure #NeuralNetworks #DistributedComputing #HPC #ModelOptimization #AIArchitecture #NvLink #Transformer #MLOps #AIEngineering #ComputerArchitecture

With Claude